Integrated circuits are typically fabricated from one or more layers of different materials. Some layers, such as polysilicon, are used to form semiconductor devices while other layers, such as patterned metal layers, provide electrical connections between semiconductor devices. Typical integrated circuits include multiple patterned metal layers, with intervening inter-level dielectric (ILD) layers to electrically insulate the metal layer.
The selection of a particular ILD depends upon the performance, density and reliability requirements of a particular semiconductor circuit. Ideal ILDs are contamination and defect free, exhibit a low dielectric constant that approaches unity, have a sufficiently high field strength, provide a good barrier to sodium ions (Na+) and provide infinite etch selectivity to underlying materials such as silicides, silicon and polysilicon. ILDs must also conform to different topographies, such as steps and gaps, exhibit good adhesion to the underlying and overlying layers and be capable of planarization. However, in fabricating ultra high density semiconductor devices which include tightly packed, high aspect ratio metal patterns, it is difficult to satisfactorily fill the gaps with and effect planarization of a deposited dielectric material. For example, many conventional semiconductor dielectric deposition techniques, such as plasma-enhanced chemical vapor deposition (PECVD), do not adequately fill sub 0.5 micron gaps, resulting in the formation of voids which contain contaminants and adversely affect circuit performance.
A prior approach to forming ILDs involves depositing two dielectric layers. For example, a first gap filling layer of spin-on-glass (SOG), high density plasma (HDP), silicon dioxide (SiO.sub.2), or other oxide, is deposited on a patterned metal layer to fill any gaps therein. Typical gap fill layers not only fill gaps but deposit a significant amount of dielectric material on top of the underlying patterned metal layer. Then a second dielectric layer, referred to as a "cap layer," is deposited on the gap fill layer. The cap layer is then planarized (leveled), as by a chemical-mechanical polishing (CMP), to provide a substantially flat upper surface on which additional layers can be formed. Such a technique is illustrated in FIGS. 1A and 1B.
Referring to FIG. 1A, a conventional integrated circuit structure is designated by the reference numeral 100. A dielectric layer 102, typically SiO.sub.2, is formed on a substrate 104, typically doped monocrystalline silicon (Si). A patterned metal layer comprising one or more metal "stacks" 105 with gaps therebetween, is formed on dielectric layer 102. Conventional metal stacks 105 are comprised of a lower barrier layer 106, typically titanium (Ti), an intermediate primary conductive layer 108, typically aluminum (Al), on barrier layer 106, and an upper anti-reflective coating (ARC) 110, typically titanium-nitride (TiN), on conductive layer 108. Barrier layer 106 and ARC 110 tend to reduce electromigration in conductive layer 108, albeit at the cost of increasing sheet resistance. The total height of a metal stack 105 is typically about one micron.
Once metal stacks 105 have been formed, a gap fill layer 112, such as SiO.sub.2, is deposited on dielectric layer 102 and ARC 110, to insulate metal stacks 105 from each other. Gap fill layer 112 characteristically contains peaks 114 above metal stacks 105 that typically have a height 116 above the upper surface of ARC 110 of about 1.0 to about 1.2 microns.
As illustrated in FIG. 1B, a cap layer 118 is deposited on gap fill layer 112. Cap layer 118 typically has a thickness of about 1.2 to about 1.8 microns. The upper surface 120 of cap layer 118 is not flat but contains peaks above peaks 114 on gap fill layer 112. As illustrated in FIG. 1C, cap layer 118 is then planarized as by CMP, so its upper surface 120 is substantially flat. The planarization of cap layer 118 typically removes about 0.2 to about 0.8 microns of dielectric material, leaving a cap layer 118 having a thickness of about one micron. Thus, gap fill layer 112 and cap layer 118 form an ILD 122 having a relatively smooth upper surface 120 upon which additional integrated circuit layers may be formed.
The conventional methodology illustrated in FIGS. 1A-1C suffers from drawbacks. Specifically, it is extremely difficult to control the final thickness of cap layer 118 using conventional CMP, because it is virtually impossible to determine the thickness of cap layer 118 during CMP with the requisite precision. Conventional practices measure the thickness of cap layer 118 between polishing intervals and estimate the amount of additional polishing needed to achieve a particular thickness. As such methodology is not particularly accurate, ILD 122 is often formed at a thickness greater than is desired, particularly when peaks 114 are relatively high. Thick ILDs are relatively more expensive to fabricate because of the additional amount of dielectric material employed and processing required.
Efforts have been made to reduce ILD thickness by reducing the height 116 of gap fill layer 112 by first depositing a thin PECVD film on metal stacks 105 and then etching the film with a CF.sub.4 plasma. Plasma processing alters ARC 110 so that the deposition rate of gap fill layer 112 on ARC 110 is reduced, thereby reducing the height of peaks 114. However, this approach undesirably raises the dielectric constant of gap fill layer 112, which can adversely affect circuit performance.
Accordingly, there is a need for a method for fabricating integrated circuits having ILDs that avoids the problems and limitations of prior approaches. There is a particular need for a method for fabricating integrated circuits enabling relatively better control of the thickness of ILDs.